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1 Layout Design Process

The electronic product panel control chip is designed by Huahong NEC0.35μm CZ6H 1P3AL process. The design goal is to minimize the chip area and reduce the cost while meeting the function. After the front-end synthesis generates the netlist, the next task is to convert the netlist into a layout. The design requirements of this project: the operating frequency is 12 MHz, the chip size (including Pad) should be as small as possible, and the power consumption should not exceed 3 mW. According to the requirements of the project, the SOC Encounter, a back-end layout and routing tool commonly used in ASIC design, is selected for layout design. Because the chip needs 80 mA to drive the LED in the digital TV set-top box, and the standard IO PAD provided in the CZ6H process cannot meet the requirements, it needs to be designed by itself. In addition, the working clock of the chip is required to be generated internally, so it is necessary to design a 50 MHz oscillator, which is divided by 4 as the working frequency. The two self-designed modules are transformed into hard macro units using Cadence company's Abstract Generator tools to start layout design. The design process of electronic product panel control chip based on SoC Encounter is shown in Figure 1.

2 Layout Design

According to the layout design process, the layout design of the electronic product panel control chip is carried out, and the specific solutions are put forward for the problems in the design.

2.1 Design Input

Design input is the preparation work before layout design. The following four kinds of files need to be input: netlist file generated by the front end, timing constraint file, hard macro cell related file and Hua Hong NEC 0.35 μm CZ6H 1P3AL process library related file provided by chip manufacturer.

The process library contains process data, physical information of library cells for automatic placement and routing, and their timing information (which defines the delay information of standard cells and input and output cells for static timing analysis). The standard cell process library is provided by Hua Hong NEC, but for the provided CZ6H_IO_3AL.lef file, the power supply VDD PAD(HQIV5A1B) and GNDPAD(QIC0A00) cannot be connected to the power supply network in Core, so the lef file needs to be modified: a line of Class Core is added to the definition of PIN VDD in HQIV5A1B, and a line of Class Core is added to the definition of GND PIN in QIG0A00 to realize connection.

In addition, the layout design tool is used to Virtuoso the oscillator and large drive current IO PAD layout drawn by Layout Editor, and the Abstract Generator tool is required to convert the layout into LEF file and timing information file required by SoC Encounter. However, for the oscillator, the power supply/ground cannot be connected to the power supply network in the Core, so the lef file needs to be modified manually: a line of Use Power is added to the definition of PIN VDD, and a line of Use Ground is added to the definition of PIN GND to realize the connection.

When the SoC Encounter tool used to generate the netlist by the DC synthesis tool is used for layout design, the power/ground PAD unit and the PADComer unit that provides power network connection for the PAD power rings on different sides need to be added to the netlist. In addition, a time constraint file will be exported after DC synthesis, which is used by the SoC Encounter tool to constrain the timing information of the place and route phase.

2.2 plane planning

Plane planning is the overall planning of the structure of the electronic product panel control chip, including defining the Core area, setting the Row structure, placing the port Pad position, placing the oscillator in the Core and designing the power network.

This design is PAD limited, and the pin arrangement sequence is fixed when the chip is packaged. In addition, the I/O PAD with 80 mA current and the standard I/O PAD have different widths. Therefore, the placement of PAD should be carefully studied to minimize the area of the chip. This design uses the preparation of I/O allocation file, providing offset (Offset) to directly specify the precise location of all I/O PADs, realizing that PADs and Comers are closely connected with adjacent PADs, without inserting any PAD Filler unit in the middle, thus achieving the minimum chip area.

In the past power network design, because there is no suitable method, usually based on experience, and the analysis and verification of the power network is usually placed after the layout design is completed. The problem is that if the power network design cannot meet the requirements, it will lead to repeated layout design, prolong the design cycle of the chip, and delay the time to market of the chip. Therefore, the design of the chip power network adopts a fast layout design process at the beginning without considering the timing convergence of the circuit, and the power consumption analysis shows that the power consumption of the chip Core is 2.873 4 mW, and then the power network is designed according to the power consumption of the chip Core. Since this design is limited by PAD, the width of the power ring is set to 15 μm after calculation and a large margin is left, and a horizontal power strip with a width of 10 μm is placed in the middle.

After the oscillator is moved inside the Core to fix its position and add a power ring to it, an error mark of "x" will appear when connecting the power supply network as shown in fig. 2. the solution to this problem is to execute the addHaloToBlock command and use Ruler to measure the distance from the oscillator to the periphery of the 4 sides and set it.

2.3 Layout

Layout is the process of placing each standard cell location in an electronic product panel control chip, which requires optimization of a specific objective function during layout, which usually includes timing, line length, congestion, and so on. This design uses a timing-driven layout to place the cells on the critical path very close to shorten the length of the connection to reduce the critical path delay. However, in order to reduce congestion, the lines should be evenly distributed on the layout to avoid local congestion, so the maximum density for layout is set to 50%. Through the timing analysis and blocking analysis, it can be seen that this approach not only achieves timing convergence, but also does not appear congestion, and the layout effect is good.

2.4 clock tree synthesis

Because all operations in the synchronous design circuit need clock control to realize synchronization, and the clock network has the largest load, the longest route and the most demanding requirements in all signal networks, the quality of clock tree synthesis directly affects the performance of the chip. The purpose of clock tree synthesis is to control clock propagation delay, clock skew and transition time. A larger clock delay is not good for solving the setup time problem of the circuit, a larger clock offset will increase the probability of the register latching unstable data, and controlling the transition time is conducive to optimizing the power consumption of the clock tree. In this design, the number of levels and the number of buffers are automatically determined according to the timing constraints in the clock tree specification file in the automatic CTS mode, and then the number of levels, buffer types and connected registers are manually modified according to the specific circumstances of the design to achieve the best possible results. By comparing the clock tree synthesis report file, it can be seen that in the automatic mode, the clock offset is 0.13 ns, and the clock offset is 0.078 ns after manual modification, and the clock tree synthesis result is displayed, as shown in fig. 3.

2.5 Wiring

SOC Encounter is completed in two stages when wiring: pre-wiring and detailed wiring. When pre-wiring, the wiring tool divides the entire chip into multiple smaller areas. The wiring device only estimates the shortest wiring length between the signals in each small area and calculates the wiring delay and the wiring congestion degree in each area. At this stage, no real layout wiring is generated. Detailed cabling takes into account signal integrity and timing drive, while repairing antenna effects, crosstalk effects, and design rule violations. The detailed wiring tool finds and repairs short-circuited and open-circuited wires, while optimizing the wiring after completion. When detailed routing, Routing Track definition, layout planning, setNanoRouteMode command parameter setting conflicts will cause line open circuit. After the open circuit condition occurs, the verifyTracks command can be used to diagnose the open circuit problem of the standard cell line, and can report the problems such as the distance between the pins inside the Blockage is too far, the pins are not aligned, the pins are under the Stripes, etc. Through the analysis of the report, understand the reasons and then adjust the layout until the problem is solved.

2.6 design for manufacturability

The manufacturability design includes eliminating antenna effect (not required by NEC0.35CZ6H process), adding Core filling cells (FILL1,FILL2), optimizing contact holes, and adding metal filling to meet metal density requirements.

By default, a single hole is used for the connection between the upper and lower layers. If space permits, double holes or porous holes can be used for connection. The purpose of using double holes or porous holes is to reduce the via resistance and reduce the failure caused by electromigration, which is conducive to timing convergence and improving yield. Routing tools will use: Multiple-cut Vias or Fat Vias to replace signal vias to optimize vias. Fix crosstalk with inserting Multi-Cut Via or Fat Vias during detailed routing.

The layout is composed of rows of high Row. Since the utilization rate of standard cells placed in Row cannot reach 100, there may be gaps of different sizes between standard cells in Row. If these gaps are not filled with filling cells, a large number of DRC violations will occur when the physical verification tool checks the design rules. The solution is to add Core filling cells (FILL2,FIL-L1).

According to the metal density filling rules in the CZ6H process, all metal layers are added with metal filling considering timing, so that metal filling can be avoided as much as possible around the clock and signal lines, and more around the power supply and ground lines.

2.7 Verification

Perform wiring verification and timing verification on the layout after the manufacturable design is executed. Connection verification includes: whether the line is connected (Verify Connectivity), whether the grid is correct (Verify Geometry), whether the metal density reaches 20%, etc. After operation, the report file can be checked, and the line-to-line spacing violation after metal filling is found, which needs to be adjusted manually.

The timing verification generates reports to check that the setup time, hold time, maximum capacitance, and maximum transition time meet the requirements and that the design meets the requirements.

2.8 power consumption, voltage drop and electromigration analysis

The power, voltage drop and electromigration analysis results of the designed layout are shown in fig. 4, from which it can be seen that the design of the number of power/ground PAD, power ring and power bar meets the requirements of power consumption, voltage drop and electromigration.

2.9 output

After the layout design is completed, the information required for back-end verification is extracted from the layout, such as Verilog netlist files for formal verification, physical verification, static timing analysis, and post-simulation, for physical verification tools. DRC,LVS and LPE after each unit GDS file Merge output GDS file. Import the generated GDS file into the Virtuoso Layout Editor tool to add the Cover unit and mark the Labe1 label at the corresponding position, and finally control the layout of the chip on the electronic product panel, as shown in Figure 5.