Back-end design of electronic product panel control chip

The electronic product panel control chip is designed by Huahong NEC0.35μm CZ6H1P3AL process. The design goal is to minimize the chip area and reduce the cost under the premise of meeting the function. After the front-end synthesis generates the netlist, the next task is to convert the netlist into a layout. The design requirements of this project: the operating frequency is 12MHz, the chip size (including Pad) should be as small as possible, and the power consumption should not exceed 3mW. According to the requirements of the project, the back-end layout and routing tool SOCEncounter commonly used in ASIC design should be selected for layout design. Because the chip drives the digital TV set-top box.